1. Field of the Invention
The present invention relates to a semiconductor logic circuit device and a wafer-probing testing method therefor.
2. Description of the Related Art
Generally, after a plurality of semiconductor logic circuit devices (chips) are formed on one wafer, a wafer-probing testing operation is performed upon each of the semiconductor logic circuit devices. As a result, only the semiconductor logic circuit devices which have passed the wafer-probing testing operation are diced and packaged, while the others are scraped.
Note that the number of pads of one semiconductor logic circuit device is considerably large, for example, 500 to 1000. Therefore, if a wafer-probing tester has pins (probes) corresponding to all the pads of semiconductor logic circuit devices, the wafer-probing tester would be considerably cost-consuming. Therefore, it is essential to decrease the number of pins (probes) of the wafer-probing tester.
A first prior art wafer probing testing method is carried out by using a probe card for connection between pads of a semiconductor logic circuit device and pins of a wafer-probing tester. In this case, the number of the pins of the wafer-probing tester is smaller than the number of the pads of the semiconductor logic circuit device, which would decrease the manufacturing cost of the wafer-probing tester. This will be explained later in detail.
In the above-described first prior art wafer-probing testing method, however, since a control circuit for controlling the probe card is incorporated into the semiconductor logic circuit device, the manufacturing cost thereof is increased. Also, since the probe card is designed specially for the semiconductor logic circuit device, the manufacturing cost of the wafer-probing tester is increased. This also will be explained later in detail.
A second prior art wafer-probing testing method is carried out by serially inputting a test input pattern (vector) into a semiconductor logic circuit device (see: JP-58-118123-A).
In the above-described second prior art wafer-probing testing method, however, since the test input pattern is serially inputted to the semiconductor logic circuit device, the test time becomes large.
A third prior art wafer-probing testing method is carried out by a probe card including a scan path between a semiconductor logic circuit device and a wafer-probing tester (see: JP-7-84009-A). As a result, a test input pattern (vector) is serially inputted to the scan path of the probe card which, in turn, transmits the test input pattern (vector) in parallel to the semiconductor logic circuit device.
In the above-described third prior art wafer-probing testing method, however, since the scan path is included in the probe card, the probe card is high in manufacturing cost. Also, since the probe card is designed specially for the semiconductor logic circuit device, the probe card is also high in manufacturing cost.